As semiconductor devices approach limits for scaling, pitch doubling and three-dimensional stacking have been considered as alternative techniques to increase device density and lower costs. While lithography limitations may be addressed via pitch doubling either by using a spacer hard mask or double patterning, contacting the less than nominal pitch features between devices at three-dimensional layers may be challenging due to critical dimension and alignment constraints.
It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.